IEC 63011-1:2018 pdf download

IEC 63011-1:2018 pdf download.Integrated circuits – Three dimensional integrated circuits – Part 1: Terminology
1 Scope
This part of IEC 6301 1 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided.
2 Normative reference
The following documents are referred to in the text in such a way that some or all of their content constitutes requirements of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies. There are no normative references in this document.
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply. ISO and IEC maintain terminological databases for use in standardization at the following addresses: • IEC Electropedia: available at http://www.electropedia.org/ • ISO Online browsing platform: available at http://www.iso.org/obp 3.1 General The general terms listed below relate to the secondary integration method in vertical direction using integrated circuits fabricated on a horizontal surface of semiconductor. 3.1.1 interposer electrical interface that connects one socket or connection to another Note 1 to entry: The purpose of an interposer is to spread a connection to a wider pitch or to reroute a connection to a different connection 3.1.2 multichip interconnect technology technology that allows for the vertical stacking of layers of basic electronic components which are connected using an interconnect fabric are as follows: Note 1 to entry: “Basic electronic components” are elementary circuit devices such as transistors, diodes, resistors, capacitors and inductors. Note 2 to entry: A special case of multichip interconnect technology is the interposer structures that may only contain interconnect layers, although in many cases other basic electronic components (in particular decoupling capacitors) 3.1.3 3-D bonding process that joins two die or wafer surfaces together multiple surfaces mechanically or electrically EXAMPLE: Die-to-die, die-to-wafer, wafer-to-wafer 3.1.4 3-D stacking 3-D bonding operation that assumes electrical interconnects between the two devices 3.1.5 3-D packaging 3-D integration of multiple dies using wire bonding, package-on-package stacking, or embedding in printed circuit boards 3.1.6 3-D wafer-level-packaging 3-D WLP 3-D integration using wafer level packaging technologies, performed after wafer fabrication, which consists of flip-chip redistribution, redistribution interconnect, fan-in chip-size packaging, and fan-out reconstructed wafer chip-scale packaging Note 1 to entry: This note applies to the French language only. 3.1.7 redistribution layer RDL extra metal layer on a chip that makes the IO pads of an integrated circuit available in other locations Note 1 to entry: This note applies to the French language only. 3.1.8 system in package SIP integration of multiple dies, packages, or mixture of them as system in a package Note 1 to entry: This note applies to the French language only. 3.1.9 3-D stacked integrated circuit 3-D approach using direct interconnects without wire bonding between integrated circuits of multiple dies Note 1 to entry: The 3-D stack uses a sequence of alternating front-end (devices) and back-end (interconnect) layers. 3.1.1 0 3-D integrated circuit 3-D IC 3-D approach using direct stacking of active devices Note 1 to entry: Interconnects are on the local on-chip interconnect levels. The 3-D stack is characterized by a stack of front-end devices, combined with a common back-end interconnect stack. Note 2 to entry: This note applies to the French language only.3.2 Test method in 3D environment 3.2.1 package stack integrated circuit packaging method to combine vertically discrete logic and memory ball grid array (BGA) packages Note 1 to entry: Two or more packages are installed atop each other. 3.2.2 package-on-package POP package in which multiple packages are enclosed Note 1 to entry: This note applies to the French language only. 3.2.3 multi-chip-package MCP package in which multiple dies are stacked vertically or placed side-by-side Note 1 to entry: This note applies to the French language only. 3.2.4 die stack chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit