IEC TR 63051:2017 pdf download

IEC TR 63051:2017 pdf download.Documentation on design automation subjects – Mathematical algorithm hardware description languages for system level modeling and verification (HDLMath)
1 Scope
A hardware description language provides a means to describe the behavior of a system precisely and concisely. This document describes the main functional requirements for an HDLMath language and compares existing HDLMath languages from the viewpoint of designers. It is intended to accelerate the standardization of a mathematical algorithm design language and to help establish a new and good system modeling and verification environment.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content constitutes requirements of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies. There are no normative references in this document.
3 Terms and definitions
No terms and definitions are listed in this document. ISO and IEC maintain terminological databases for use in standardization at the following addresses: • IEC Electropedia: available at http://www.electropedia.org/ • ISO Online browsing platform: available at http://www.iso.org/obp
4 Definition and positioning of HDLMath
4.1 General HDLMath is defined as a language for describing and verifying the behavior of an entire system or product using mathematical algorithms. IEC TR 62856:201 3 (BVDL) describes the features of existing design languages used in the design processes applied to the development of System-on-Chip (SoC) devices, which range from system level design, IP block creation and analog block design, to SoC design implementation and verification. HDLMath will cover system level design in the BVDL schema.4.2 Current HDLMaths Currently, there are three kinds of language for these design environments: HDLMath1 , HDLMath2, and HDLMath3. HDLMath1 is a kind of high-level language that has an interactive environment for numerical computation, visualization, and programming. It is able to analyze data, develop algorithms, and create models and applications using the language, tools, and built-in mathematical functions. It features the following:a) a block diagram environment for multi-domain simulation and model-based design; b) simulation, automatic code generation, and continuous test and verification of embedded systems. HDLMath2 is motivated by the need for mathematical modeling within the Verilog language. Its features are as follows: • no explicit conversion functions are necessary; • support for runtime changes of formats, including the number of bits of the various fields; • data in multi-dimensional arrays that are easy to access globally. The language is designed to support a large number of mathematical system tasks, and provides access to information regarding the occurrence of overflows, underflows, maximum number of bits needed, cumulative error, etc. HDLMath3 is a language mainly to support analog design. It allows networks of analog parts such as resistors, capacitors, etc., to be defined. The simulator extracts the differential equations corresponding to the network of analog parts and solves them based on initial conditions and using a timestep provided by the user. It is able to handle blocks that are modeled mathematically and written at the C/C++ level. However, the mathematical capabilities in math.h (a kind of C function library) are limited at the low level of C/C++ and not at the high levels found in HDLMath1 or HDLMath2.4.3 Design abstraction level of HDLMath Figure 1 shows the number of lines of code for several small examples written using HDLMath1 and HDLMath2. It also shows the length of the C-code generated automatically from an HDLMath1 description. The number of lines of C-code is several hundred times larger than that of the HDLMath descriptions. The figure indicates how HDLMath languages can be used to design at a higher level of design abstraction and hence how design productivity is higher than C level design.